The present invention pertains to semiconductor processing, and more particularly to a dry lithographic silylation plasma etch process.
There is an ever-increasing need to improve the resolution of lithographic processes in semiconductor device fabrication. Existing processes include the use of liquid chemicals to remove photoresist after it has been exposed to form a photoresist pattern. However, such wet processes are isotropic, and cause the edges of the photoresist pattern to be undercut by an amount that depends on photoresist thickness, age, the curing process, and exposure. This effect can cause considerable variation in the size of the photoresist patterns used in forming the structure of a semiconductor device. As the required critical dimensions of the photoresist patterns decrease, this problem becomes more acute.
With the high numerical aperture (NA) lenses necessary for performing state-of-the-art deep sub-micron photolithography, the depth of focus is rather small, i.e., less than 1 micron. This is because the depth of focus is inversely proportional to the square of the NA, while the resolution is proportional to the NA. In certain situations, the depth of focus of a lens having sub-micron resolution may be less than the thickness of the photoresist layer in which a pattern is to be formed. This can cause the resultant photoresist pattern to be less than ideal i.e., have non-vertical sidewalls.
Silylation is a dry lithographic process that includes forming a very thin, usually patterned, layer of oxidized silicon on the surface of a photoresist layer deposited atop a substrate such as a silicon wafer. To form this thin oxide layer, the photoresist layer is selectively exposed (e.g., through a mask) with actinic radiation (e.g., UV light or an electron beam), thereby forming portions of exposed and unexposed photoresist. After exposure, the photoresist is treated with a silicon-containing silylation reagent. The silicon-containing reagent diffuses and reacts with the surface of the exposed region of the photoresist, but not the un-exposed regions, thereby forming select regions of silylated photoresist on the surface of the photoresist layer.
With reference to FIG. 1A, there is shown a substrate 10 having thereon a photoresist layer 16 with an upper surface 18, with silylated resist portions 20 formed in the resist layer at the upper surface. The success of the dry developing process requires that the etch is highly selective in preferentially etching the unsilylated resist, and the etch is anisotropic such that it generates a vertical etch profile. In general, this requires good control of ion energy, ion flux and radical flux towards the photoresist layer. With reference now also to FIG. 1B, when the structure of FIG. 1A is etched using a conventional dry-etched silylation process, a photoresist pattern 32 with side-walls 36 and a cap layer 40 of SiOx can result at the silylated resist portions. In this case, the resist removal process is isotropic (i.e. acts uniformly in all directions) due to a high radical flux and low ion flux. Because there is an etch-resistant cap layer 40 atop photoresist 16, the photoresist underlying the cap layer 40 is unevenly removed, resulting in photoresist pattern 32 having curved sidewalls 36, such as shown in FIG. 1B. Under such conditions, the acceptable etch selectivity is attained, however, at the expense of non-vertical side-wall profiles (i.e. there are too few ions to produce a directional etch). Alternatively, in an attempt to increase the relative ion flux, one inherently increases the ion energy as well. While achieving vertical side-wall profiles, this, in turn, leads to the etching of both the hard mask (i.e. SiOx layer) and the unsilylated photoresist regions (poor selectivity). Both cases adversely affect process control and ultimately, the performance of the semiconductor device being fabricated. Either of these effects is commonly observed in conventional dry developing silylation processes.
There are several prior art patents pertaining to dry processes in the fabrication of semiconductor devices. For example, U.S. Pat. No. 5,700,628 describes an all-dry microlithography process, where a fluorinated layer is deposited on a processable layer of a semiconductor wafer, and regions of the fluorinated layer are exposed to a masked radiation source so that exposed regions and unexposed areas are formed in the fluorinated layer. An oxide layer is grown on the fluorinated layer, forming a thicker region of oxide on the unexposed areas of the fluorinated layer, and forming thinner regions of oxide on the exposed regions of the fluorinated layer. The oxide layer is then etched, removing thinner regions of the oxide layer but leaving at least a fraction of the thicker portions of the oxide layer to be used as a patterned hard mask. Then, the exposed fluorinated layer not covered by the patterned oxide hard mask is etched to expose areas of the processable layer not covered by the oxide hard mask, for subsequent patterned processing. The subsequent patterned processing may be an etch process for pattern transfer to the processable layer, a doping process to dope the exposed regions of the processable layer, or another process such as a deposition step. The all-dry lithography process can be completed in an integrated environment, such as a cluster tool, resulting in improved manufacturing cycle time and increased yields. The dry photo-sensitive layer may be deposited using PECVD at low temperatures, and is compatible with all other semiconductor device fabrication, process flows. However, a shortcoming of this invention is that it involves a large number of processing steps, which consumes a large amount of time, which reduces device manufacturing throughput.
U.S. Pat. No. 5,366,852 describes a process for treating photoresists and forming photoresist relief images, the process comprising the steps of providing a photoresist coating having a cross-linked surface layer, treating the photoresist coating with an organo-metallic material, and developing the photoresist coating to provide a relief image comprising an etch resistant effective amount of organo-metallic material.
U.S. Pat. No. 5,362,606 describes an invention in which a resist exposed to a micron or sub-micron pattern of highly absorbed ion beams forms a highly crosslinked barrier layer in the exposed regions of the resist surface. The complementary surface regions are silylated in a silicon-containing reagent, and the exposed regions are then removed by a plasma etch. Pattern definition is enhanced by limiting the exposure and the silylation to the surface of the resist. The process allows feature definition below 1000 Angstroms using a relatively inexpensive single element low energy ion source. However, a shortcoming of this invention is that it utilizes an oxygen reactive ion etch (RIE) reactor with characteristically a low density of high energy ions (energies of order 200 eV), which is not desirable because the ion energy is sufficient to exceed the sputter threshold of the SiOx hard mask (i.e., the hard mask is sputter etched).
U.S. Pat. No. 5,562,801 describes a process of etching an oxide layer. First, a resist layer is formed on an oxide layer on a substrate. Next, a photo-sensitive layer is formed on the oxide layer and patterned to expose regions of the oxide layer to be removed. The exposed regions may overlie a nitride layer, and may overlie a structure such as a polysilicon gate. The etch is performed such that polymer deposits on the photo-sensitive layer, thus eliminating interactions between the photo-sensitive layer and the plasma. In this way, a simple etch process allows for good control of the etch, resulting in reduced aspect ratio dependent etch effects, high oxide:nitride selectivity, and good wall angle profile control. However, a shortcoming of this invention is that it requires a relatively large number of process steps and includes the formation of numerous layers of material, which adds cost and complexity to the process.
The present invention pertains to semiconductor processing, and more particularly to a dry lithographic silylation plasma etch process.
A first aspect of the invention is a process of plasma etching a substrate having an upper surface coated with a first layer of silylatable material with one or more silylated regions formed therein. The plasma is oxygen-based and has a first region with a low plasma density and high radical density, and a second region having a high plasma density and a low radical density. The process comprises the steps of exposing the one or more silylated regions to the first plasma region to form respective one or more oxidized regions from the one or more silylated regions. The next step is then exposing the substrate to the second plasma region to selectively etch the silylatable material directly exposed to the plasma.
A second aspect of the invention is the process as described above, wherein the process is carried out in the chamber of a plasma processing system, and further includes at least one of the following steps in adjusting the process:
a) adjusting an amount of RF power coupled to the second plasma region;
b) adjusting an RF bias applied to the substrate;
c) adjusting a flow of a gas (e.g., oxygen) to the plasma;
d) adjusting the pressure within the chamber; and
e) varying the position of the substrate within the chamber.